Bipolar transistors with control of electric field

ABSTRACT

The invention provides a bipolar transistor circuit and a method of controlling a bipolar transistor, in which the bipolar transistor has a gate terminal for controlling the electric field in a collector region of the transistor. The bias voltage applied to the gate terminal is controlled to achieve different transistor characteristics.

This invention relates to bipolar transistors, and in particular bipolartransistor designs which make use of a control terminal (additional tothe base, collector and emitter terminals), for controlling the electricfield distribution within a portion of the device.

In the field of data communications, there is an on-going need for poweramplifiers that are able to operate at high speed. Systems of this kindtypically use power amplifiers at the transmitter side to enable them totransfer the data from the circuit to the open field by electro-magneticradiation. These high-frequency power amplifiers are designed to work athigh currents and/or high voltages in order to transmit sufficientpower.

Although CMOS based technologies can be used to produce high outputpower amplifiers, bipolar technologies remain important for providinghigh-efficiency, high power amplifiers at (ultra-) high frequencies.There is often a trade-off in bipolar devices between high powerperformance, high frequency performance and cost.

For bipolar technologies, high currents can be obtained with large-areatransistors, while the breakdown voltage of the device largelydetermines the maximum voltage swing during operation.

When the technical requirements for medium RF power amplifiers becomemore stringent in terms of output power, power gain and linearity, newdesigns of cost-effective bipolar or heterojunction bipolar transistors(HBT) are required to meet these criteria. The aim would be to enable Sior SiGe HBT's with characteristics comparable to expensive GaAstransistors.

It has been proposed to use control of the electric field distributionin a bipolar transistor to enhance the trade-off between breakdownvoltage and other device characteristics, for example as disclosed inU.S. Pat. No. 6,777,780.

The structure described has a drift region, and one or more gatecontacts, which enable to shape the electric field in the collectorregion proximal to the base region. This enables a uniform electricfield to be shaped enables the range over which the field is constant tobe varied. As such the setting point for the trade-off between variousbipolar transistor characteristics can be set.

According to the invention, there is provided a transistor circuit,comprising:

a bipolar transistor comprising a base, collector and emitter, and oneor more gate terminals for controlling the electric field in a collectorregion of the transistor;

a control circuit for controlling the bias voltage or voltages appliedto the gate terminal or terminals, with different control voltages usedfor different transistor characteristics.

The ability to provide different transistor characteristics by setting acontrol voltage enables different identical transistors to havedifferent Is characteristics. The control voltage can be static so thatthe circuit is configured in a certain way to achieve the desiredperformance.

A system can then have multiple identical transistors but with differentstatic bias applied. Different bias settings can be used in a systemcomprising many transistors. Depending on the configuration, therequirement of breakdown voltages (BV) and speed (cut-off frequency fT)for these transistors might be different. By setting different gatebiases for identical transistors, they can have differentcharacteristics. For example, with two identical transistors, one canhave BV1 and fT1 with control voltage VG1; and another have BV2 and fT2with control voltage VG2.

An example of multiple transistors is a cascaded configuration where onetransistor needs a high breakdown (but does not need an extremely highfT) while the other transistor needs a high speed (high fT) and notnecessarily a high breakdown. In such configuration, the sametransistors can be used but with different static biasing on the gate tomake them operate in the regime as needed in the cascade circuit.

Alternatively, the control voltage can be dynamic. The gate terminalassociated with the collector can be considered to be a field plate, andthis can be used to further advance the power capability of such adevice. By biasing the gate terminal dynamically, the power capabilityof the device can be extended by pushing the load line outwards so thatboth V_(CE,MAX) and I_(C,MAX) can be increased. The circuit can be tunedto a particular application by selecting the bias voltage.

The circuit can further comprise:

a feedback circuit for dynamically controlling a bias voltage applied tothe gate terminal in dependence on a collector-emitter or base-emittervoltage of the bipolar transistor.

This enables the circuit to respond dynamically to the circuitconditions.

The feedback circuit preferably comprises a signal processing unit forgenerating a bias voltage which related to the collector-emittervoltage. In this way, by an appropriate field shaping, the highbreakdown (for high voltage operation) or high current (for smallercollector emitter voltage) can be is achieved.

The feedback circuit can comprise an inverter connected between thecollector and gate terminal.

The dynamic control is preferably at the frequency of operation of thebipolar transistor so that it can respond dynamically to the loadconditions.

The circuit can be used in an RF power amplifier.

The invention also provides a method of controlling a bipolar transistorcomprising a base, collector and emitter, and one or more gate terminalsfor controlling the electric field in a collector region of thetransistor, wherein the method comprises:

controlling the bias voltage or bias voltages applied to the gateterminal or terminals to achieve different transistor characteristics.

Examples of the invention will now be described in detail with referenceto the accompanying drawings, in which:

FIG. 1 shows the trade-off between breakdown voltage and frequency ofdifferent high-voltage SiGe heterojunction bipolar transistors (HBTs);

FIG. 2 shows an example of bipolar transistor structure to which theinvention can be applied;

FIG. 3 shows how the accumulation layer under a collector field platechanges with various gate voltages at the ON state;

FIG. 4 shows the value of the collector-base breakdown voltage atvarious values of the field plate voltage;

FIG. 5 shows an adjustable relationship between frequency and breakdownvoltage with varied field-plate voltages;

FIG. 6 shows how dynamic switching of the field-plate allows to use adifferent load line which is more in favour for better power operation;and

FIG. 7 shows an example of how to implement dynamic field plate voltagecontrol in a power amplifier.

The invention provides a bipolar transistor circuit in which the bipolartransistor has one or more gate terminals for controlling the electricfield in a collector region of the transistor. The bias voltage orvoltages applied to the gate terminal or terminals are controlled toachieve different transistor characteristics.

In example the control is static, so that different identicaltransistors in a circuit can have different (fixed) characteristics. Inanother example, a feedback circuit dynamically controls a bias voltageapplied to the gate terminal in dependence on a collector-emitter orbase-emitter voltage of the bipolar transistor. This enables thetransistor performance to be tuned in real time to the dynamicallyvarying load requirements.

Bipolar (or heterojunction bipolar) transistors are currently used forRF power amplifiers at high frequencies thanks to their good RFcharacteristics. For such applications, a high-breakdown device isusually preferred allowing high voltage swing at the output (for highoutput power). However, high voltage devices usually have theirlimitations, which include:

(i) A low speed. There is always a trade-off between breakdown voltageand speed: a high-breakdown voltage device has a low f_(T) (thefrequency at which the current gain is unity) and vice versa. FIG. 1shows a general example of such a trade-off and shows different devicesof different collector emitter breakdown voltage (BVceo).

(ii) Current limitations. As can be seen FIG. 1, there is a relationbetween speed (fT) and maximum current (i.e. current at peak fT). Thiscurrent is shown as J_(MAX), it means that the high-voltage devicesuffers also from a lower J_(MAX), which makes the power capability ofthe device also lower.

In practice, different breakdown voltages and fT values for differentapplication requirements are obtained by changing the process for thecollector profile (i.e. implantation dose, implementation energy,diffusion time and io temperature). This complicates the process orincreases its cost and limits the flexibility of the designer inimplementing ICs.

As mentioned above, it has been proposed to use one or more gate biasesto increase the flexibility and power capability for power bipolardevices.

This invention will be described in connection with a particular bipolarIs transistor design which will now be described. The invention ishowever not limited to the particular transistor shown.

FIG. 2 shows one example of bipolar transistor structure to which theinvention can be applied. The method of the invention of using an extraterminal (for example to dynamically extend the power capability of thedevice) can be applied to any bipolar device as long as that device hasa contact close to the collector drift region. The structure of FIG. 2is one example.

The transistor has an emitter E, a base B and a collector C. The emitterE is formed in the bulk of the substrate of the device. The emitter Ecould also be formed as a layer above the surface of the substrate.

The base B is provided as a layer of semiconductor material over theemitter E. The layer forming the base B can be deposited and patternedusing standard lithographic techniques, to provide the desireddimensions and alignment with respect to the emitter E. The collector Ccan also be provided as a patterned layer of semiconductor material,dimensioned and aligned with respect to the base as desired.

In the example structure of FIG. 2, the collector C extends laterally ina plane substantially parallel to the major surface of the substrate.The collector C overlaps the base B (thereby to make contact therewith),but also extends past an edge of the base B and away from theoverlapping region. To prevent a short circuit of the base B adielectric 10 is provided beneath the overhang portion of the collectorC to ensure that this portion of the collector C does not make contactwith the emitter E. The collector C is formed at the “top” of the device(i.e. above the emitter E and the base B). The emitter E, base B andcollector C are each provided with corresponding emitter contact(s) 12,base contact(s) 14 and collector contact(s) 16 The collector C isprovided with a collector gate 18. The purpose of the collector gate 18is to shape the electric field within the collector C. The collectorgate is thus a gate terminal of the device, in addition to theconventional base, emitter and collector terminals. It functions as afield plate. In this way, the peak electric field within the collector Ccan be suppressed, thereby improving still further the breakdown voltageof the device. This field shaping in this device thus makes use of acollector gate in a bottom-up bipolar transistor having a lateralcollector.

Although a small gate is shown schematically in FIG. 2, in principle thegate can also be extended laterally over the entire collector region.This can give improved field shaping.

This invention relates to biasing of the gate, and it can be applied todifferent transistor designs, such as vertical transistors. It can beapplied to any structure which implements a gate which enables fieldshaping in the drift region.

In high-power devices, it is known that a field plate can be used toreshape the field distribution. With a suitable bias, an accumulationlayer can be formed under the field plate, which can be used forenhancing f_(T) and current.

In order to understand the behaviour of the accumulation layer underdifferent field plate bias (V_(G)) for the field plated-collector ofFIG. 2 a CAD model has been used.

The impact of field plate voltage has then been investigated at ON andOFF states:

In the ON state (for example: V_(CE)=1V, VBE=0.7V): when V_(G) increasesfrom 1V to 10V, the accumulation layer under the field plate starts toincrease and extend under the whole field plate (to a saturation level).FIG. 3 shows how the accumulation layer under the field plate (at X=−0.5μm) changes with various gate voltages at the ON state. Thisaccumulation layer can be considered as a thin collector (i.e.,virtually moving the collector closer to the base), which helps delaythe onset of the Kirk effect and increase f_(T). In brief, high f_(T)and low BVceo are obtained at high V_(G).

In the OFF state (V_(CE)=1V, VBE=low voltage for example 0V): when V_(G)increases from 1V to 10V, the breakdown BVcbo is reduced, which can beexplained as follows. At a low V_(G) and high V_(CE), the field ispushed away from the base-collector junction (or lines of equi-potentialare pushed further to the end of collector), which is beneficial for ahigh breakdown. When V_(G) is increased, that effect is reduced (e.g.the collector is depleted slower) which makes the breakdown voltagelower. FIG. 4 shows the value of BVcbo at various values of the fieldplate voltage V_(G). (V_(G)=1, 4, 7, 10 V).

The transistor has two main important figures of merit: breakdownvoltages (BVcbo) and cut-off frequency (fT). While BVcbo is determinedat the OFF-state condition, fT is determined at ON-state condition. In amethod which dynamically changes breakdown voltages (BV) and fT, ananalysis of the effect of bias at these ON and OFF states is relevant.The bias conditions mentioned above for ON and OFF states (e.g., VCE=1V,VBE=0.7V; VCE=1V, VBE=0V) are of course simply a typical example ofbiasing for a silicon-based bipolar transistor. Other bias conditionsare possible.

There are various applications of this control of the accumulationlayer.

A first application is to create a single design of device with variousvalues of f_(T) and breakdown voltage. This can be considered to be astatic implementation of the invention, in which different transistorsin a multiple-transistor circuit are biased to provide differenttransistor characteristics.

By making use of the effect described above relating to the accumulationlayer, one device can be made with an f_(T) and breakdown (BVceo andBVcbo), which can be adjusted by varying only the field-plate bias.

FIG. 5 shows an adjustable f_(T)/BVceo with varied field-plate voltages.

As shown in FIG. 5, by increasing V_(G) from 1V to 7V, BVceo is reducedfrom 9.5V to 5V; and then increases from 20 to 32 GHz.

This shows that depending on the gate biasing it is possible totrade-off fT with BV (most clearly, seen in FIG. 5 b).

By adapting the gate voltage, the breakdown voltage and f_(T) andf_(MAX) can be adapted (with fT and f_(MAX) going up when BV is goingdown). As such, the same design of device can be used either as alower-frequency-higher-voltage device or as ahigh-frequency-lower-voltage device.

In the static implementation, a DC bias is applied to the gate which canbe a single gate or a gate which is by split into parts. One or moregates can be used for optimal field shaping. A gate part closer to thebase-collector junction can be used to shape the field for control ofthe breakdown. Different gates can be provided with different staticbias levels.

A designer can have more flexibility to apply a given transistor type tothe desired application. If it is a wireless infrastructure application,the supply voltages can be as high as 5V or 9V, while frequency bandsare 900 MHz, 2.1 GHz, 2.4 GHz, 3.5 GHz and 5.8 GHz.

In this way, separate technologies are no longer needed for differentfrequency bands—for example, one for frequencies below 2.7 GHz andanother for frequencies above 2.7 GHz.

In summary, the technology using gated HBTs can cover:

(i) High gain at different frequency bands (wide band design) at a fixedbreakdown.

(ii) High linearity over frequency and wide band (because of high f_(T))by using negative feedback designs with high loop gain.

(iii) The field-plated HBT can be universal for different applications.Depending on application requirements, it can be used with high supplyvoltages to obtain high linearity, power levels or efficiency.

(iv) More design flexibility is provided, as the field-plated HBTs canbe used with different V_(G), which is dependent on the design topology.

This application provides static control of the bias voltage, independence on the intended use of the transistor. Different biasvoltages can be used to create different transistor characteristics tosuit the intended circuit application.

A second application is to enable selection of a particular load linefor power amplifiers in a dynamic way.

The power capability (and also linearity) of power amplifiers isdetermined by the maximum voltage (e.g. BVceo or BVcbo) and maximumcurrent.

FIG. 6 shows how the load line can be shifted by biasing the field-platein real-time (at the same speed as collector).

The desired load line can be selected by the dynamic switching approach.With a better load line, better linearity can be obtained as well.

This means that in a first region (shown as Region I), where a highbreakdown is needed, a small V_(G) is applied and a high BVceo (and alsoBVcbo) can be obtained. In a second region (shown as Region II), where ahigh current is needed, a large V_(G) is applied (breakdown is notimportant here).

FIG. 6 shows two load lines 30,32. The original load line is shown as 30and the improved load line under dynamic switching is shown as 32.

The biasing does not change the load line, instead the load line is achoice made by the designer.

Starting with a given transistor, the designer chooses a load which fitsthe requirements and generates enough power and linearity. This meansthat the loadline is fixed and determined by the load impedance, e.g.loadline 30. However, to have improved performance (e.g. more power) thedesigner would like to use a different load impedance to end up with theloadline 32, but the loadline 32 crosses the breakdown voltage limit(VCE,MAX on x axis) and the maximum current (JMAX on y axis).

The dynamic control of the invention enables the designer not to becontrained by the maximum voltage and maximum current, so that a loadimpedance can be used that gives loadline 32, even if the breakdownvoltage or maximum current of the transistor is lower than thecorresponding VCE,MAX and MAX. The transistor can be tuned to allow morecurrent or voltage if the transistor is kept in the correct position onthe loadline.

In a standard transistor, the designer can only use load line 30 becauseof the maximum VCE,max and Jmax values.

The dynamic biasing approach enables the designer to use load line 32because with the circuit operated with the correct dynamic biasing, bothVCE,max and Jmax will shift, and the transistor will adapt its point ofoperation in real time to remain at a suitable point on the selectedloadline.

The power and linearity performance of power amplifiers is limited byJmax and VCE,max (of the transistor). The invention enables both Jmaxand VCE,max to be increased. The power and linearity performance of thepower amplifier by enabling the user of load line 32 will be better thanwhen there is only the choice of load line 30

This way of biasing the field plate means the power capability of thedevice can be extended by pushing the load line further to the righthand side, i.e. both V_(CE,MAX) and I_(C,MAX) can be increased. Thisenhancement is a large advantage to the current status of power(high-voltage) devices, where I_(C,MAX) is often traded off versusV_(CE,MAX)

This approach can be applied in mobile phone power amplifiers. Sincethese amplifiers are adaptively biased to get more effective currentconsumption and high power efficiency, V_(G) can be regulated so thatwhenever the power amplifier transistor experiences a high V_(out)(peak-to-peak), the high output voltage can be detected and V_(G) can bereduced in order to increase the breakdown voltage.

Power amplifiers tend to work sometimes with a mismatch at the output,i.e. the real or imaginary parts of the load can vary. Thus the outputvoltage swings can increase substantially and some part of the power isreflected back to the power amplifier. Only a certain part of the poweris still transmitted to the load. In this case a fast detection couldset up a low V_(G), extend the breakdown and the transmission would besupported without any breakdown. In a power amplifier, a very highBV_(CBO) is needed, for example 3 times larger than the operatingvoltage, to withstand very high output voltages in some unexpected casesof mismatch. However, using a high breakdown voltage transistor justthese cases, there is a consequent sacrifice of other features (e.g.high fT or Jmax). The dynamic switching method can be used withdetection of the mismatch case, and immediately the gate voltage can belowered. In this way, a higher By can be tolerated, whereas in normalsituations, we can a higher VG is used.

An example of implementing dynamic switching operation in a poweramplifier is shown schematically in FIG. 7.

FIG. 7 shows the power transistor 40 with the field plate gate G. Thereare thus four device terminals: base (B), emitter (E), collector (C) andgate (G). A substrate contact is also possible, but not essential. The(complex) load 42 is connected to the collector via a DC blockingcapacitor 44. The transistor base is DC biased by a bias circuit 47 andthe RF input is supplied through a decoupling capacitor 48.

A choke inductor 49 is connected between the power supply line and thetransistor 40. The choke 49 is used for decoupling DC and AC signals.

This is just one way of operating a power transistor, many otherconfigurations are possible and the dynamic switching of the inventioncan again be applied.

The gate biasing is implemented by a high-speed inverter 46 which probesthe collector-emitter voltage of the power transistor in real-time andsends this inverted signal to the gate of transistor 40. In this way,the gate biasing is low in the case of a high V_(CE) (region I in FIG.6) while it is high for low V_(CE) (region II in FIG. 6). Thebase-collector voltage can also be used as the feedback parameter.

There are other ways of sensing a voltage on the transistor and feedingit to the gate. For example, the base current can be probed or thevoltage swing. Since there is a relation between base and collectorcurrent and voltages, probing the base could also be used to bias thegate.

Sensing the output signal in a real-time mode for power amplifiers athigh frequencies (GHz range) has been demonstrated for example inYoung-Sang Jean et al., “High-Efficiency Power Amplifier Using NovelDynamic Bias Switching”, IEEE Transactions of Microwave Theory andTechniques, vol. 55. No. 4, April 2007 for class-E type operation.

Other power amplifiers configurations are possible as well but have asimilar way of dynamic gate-biasing as shown schematically in FIG. 7.

For example, as mentioned above, the gate can be physically split in oneor more sections (i.e. more gates next to each other on the samecollector region) with every section individually biased depending onthe application requirements or device operation.

The invention in this second application thus provides an approach fordynamically biasing the field plate of bipolar devices to enable adynamic change (i.e. adjustability) of device characteristics and theirtrade-off such as breakdown voltage (BVcbo/BVceo) vs. frequency(f_(T)/f_(MAX)). This extends the power capability and linearity of thedevice by varying V_(G) in real time, for example at the same speed asthe collector-emitter voltage swing.

Other variations to the disclosed embodiments can be understood andeffected by those skilled in the art in practicing the claimedinvention, from a study of the drawings, the disclosure, and theappended claims. In the claims, the word “comprising” does not excludeother elements or steps, and the indefinite article “a” or “an” does notexclude a plurality. The mere fact that certain measures are recited inmutually different dependent claims does not indicate that a combinationof these measured cannot be used to advantage. Any reference signs inthe claims should not be construed as limiting the scope.

1. A transistor circuit, comprising: a bipolar transistor comprising abase, collector and emitter, and at least one gate terminal forcontrolling the electric field in a collector region of the transistor;a control circuit for controlling a bias voltage or bias voltagesapplied to the gate terminal or gate terminals, with different controlvoltages used for different transistor characteristics.
 2. A circuitcomprising: at least first and second first transistor circuits asclaimed in claim 1, wherein the transistors of the first and secondfirst transistor circuits are identical and have different bias voltagesapplied to them to achieve different transistor characteristics.
 3. Acircuit as claimed in claim 1, further comprising: a feedback circuitfor dynamically controlling a bias voltage applied to the gate terminalin dependence on a collector emitter or base-emitter voltage of thebipolar transistor.
 4. A circuit as claimed in claim 3, wherein thefeedback circuit comprises an inverter connected between the collectorand gate terminal.
 5. A circuit as claimed in claim 2, wherein thedynamic control is at the frequency of operation of the bipolartransistor.
 6. An RF power amplifier comprising a circuit as claimed inclaim
 1. 7. A method of controlling a bipolar transistor comprising abase, collector and emitter, and at least one gate terminal forcontrolling the electric field in a collector region of the transistor,wherein the method comprises: controlling a bias voltage or biasvoltages applied to the gate terminal or terminals to achieve differenttransistor characteristics.
 8. A method as claimed in claim 7,comprising controlling first and second first transistor circuits,wherein the transistors of the first and second first transistorcircuits are identical, and the method comprises applying different biasvoltages to the transistor of the first and second first transistorcircuits to achieve different transistor characteristics.
 9. A method asclaimed in claim 7, further comprising dynamically controlling a biasvoltage applied to the gate terminal in dependence on a collectoremitter voltage of the bipolar transistor.
 10. A method as claimed inclaim 9, comprising generating a bias voltage from an inverted versionof the collector voltage.
 11. A method as claimed in claim 9, whereinthe dynamic control is at the frequency of operation of the bipolartransistor.